KSZ8041NLJ View Datasheet(PDF) - Micrel

Part Name

Description

Manufacturer

KSZ8041NLJ

10/100 Ethernet Transceiver with Extended Temperature Support

Micrel 

Micrel, Inc.

KSZ8041NLJ

Pin Number

31

Pin Name

LED1 /

SPEED

Type(1)

Ipu/O

Pin Function

LED Output: Programmable LED1 Output /

Config Mode: Latched as SPEED (register 0h, bit 13) during power-up / reset.

See “Strapping Options” section for details.

The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as

follows.

LED mode = [00]

Speed

Pin State

10BT

H

100BT

L

LED Definition

OFF

ON

LED mode = [01]

Activity

Pin State

No Activity

H

Activity

Toggle

LED Definition

OFF

Blinking

LED mode = [10]

Reserved

32

PADDLE

RST#

GND

LED mode = [11]

Reserved

I

Chip Reset (active low)

Gnd

Ground

Notes:

1. P = Power supply.

Gnd = Ground.

I = Input.

O = Output.

I/O = Bi-directional.

Ipd = Input with internal pull-down (40K +/-30%).

Ipu = Input with internal pull-up (40K +/-30%).

Opu = Output with internal pull-up (40K +/-30%).

Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.

2. MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII.

RXD[3..0] is invalid when RXDV is de-asserted.

3. RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered

data are sent from the PHY.

4. MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through

the MII. TXD[3..0] has no effect when TXEN is de-asserted.

5. RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which TX_EN is asserted, two bits of data are

received by the PHY from the MAC.

April 2010

9

M9999-040110-1.0

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