KSZ8001S(2005) View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
KSZ8001S Datasheet PDF : 44 Pages
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KS8001
Pin Number
36
37
38
39
40
41
42
43
44
45
46
47
48
Pin Name
GND
REXT
VDDRCV
GND
TX-
TX+
NC
NC
GND
XO
XI
VDDPLL
RST#
Type (Note 1)
Gnd
I
Pwr
Gnd
O
O
Gnd
O
I
Pwr
Ipu
Micrel
Pin Function
Ground
External resistor (6.65K Ω) connects to REXT and GNDRX
Analog 3.3 V power supply (See “Circuit design ref for power supply”
section for details)
Ground
Transmit Outputs
Differential transmit output for 100BASE-TX/FX or 10BASE-T
Transmit Outputs
Differential transmit output for FX, 100BASE-TX/FX or 10BASE-T
No Connect
No Connect
Ground
XTAL feedback
Used with XI for Xtal application.
Crystal Oscillator Input
Input for a crystal or an external 25 MHz clock
Analog PLL 1.8 V power supply
Chip Reset
Active low, minimum of 50 us pulse is required
Note 1:
Pwr = power supply;
Gnd = ground;
I = input;
O = output;
I/O = bi-directional
Ipu = input w/ internal pull up;
Ipd = input w/ internal pull down;
Note 2:
Ipu/O = input w/ internal pull up during
reset, output pin otherwise;
Ipd/O = input w/ internal pull down during
reset, output pin otherwise;
PD = strap pull down;
PU = strap pull up;
MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0]
presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted.
Note 3:
RMII Rx Mode: The RXD[1..0] bits are synchronous with REF_CLK. For each clock period in which
CRS_DV is asserted, two bits of recovered data are sent from the PHY.
Note 4:
SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100MBit mode, each
segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times; therefore,
every ten segments represents a new byte of data. The MAC can sample any one of every 10 segments in
10MBit mode.
Note 5:
MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD [3..0]
presents valid data from the MAC through the MII. TXD [3..0] has no effect when TXEN is de-asserted.
Note 6:
RMII Tx Mode: The TXD[1..0] bits are synchronous with REF_CLK. For each clock period in which TX_EN
is asserted, two bits of recovered data are recovered by the PHY.
Note 7:
SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100MBit mode,
each segment represents a new byte of data. In 10MBit mode, each segment is repeated ten times;
therefore, every ten segments represents a new byte of data. The PHY can sample any one of every 10
segments in 10MBit mode.
May 2005 – SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
MICREL CONFIDENTIAL. DO NOT DISTRIBUTE.
9
KS8001
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