KSZ8051MLL View Datasheet(PDF) - Micrel
Part Name
Description
Manufacturer
KSZ8051MLL Datasheet PDF : 51 Pages
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Micrel, Inc.
KSZ8051MLL
Pin Description – KSZ8051MLL
Pin Number Pin Name
Type(1) Pin Function
1
GND
Gnd
Ground
2
GND
Gnd
Ground
3
GND
Gnd
Ground
4
VDD_1.2
P
1.2V core VDD (power supplied by KSZ8051MLL)
Decouple with 2.2uF and 0.1uF capacitors to ground, and join with pin 31 by power
trace or plane.
5
NC
-
No connect
6
NC
-
No connect
7
VDDA_3.3
P
3.3V analog VDD
8
NC
-
No connect
9
RXM
I/O
Physical receive or transmit signal (- differential)
10
RXP
I/O
Physical receive or transmit signal (+ differential)
11
TXM
I/O
Physical transmit or receive signal (- differential)
12
TXP
I/O
Physical transmit or receive signal (+ differential)
13
GND
Gnd
Ground
14
XO
15
XI
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
16
REXT
I
Set PHY transmit output current
Connect a 6.49KΩ resistor to ground on this pin.
17
GND
Gnd
Ground
18
MDIO
I/O
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open-drain like, and requires an external 1.0KΩ
pull-up resistor.
19
MDC
I
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
20
RXD3 /
Ipu/O
MII Mode:
MII Receive Data Output[3](2) /
PHYAD0
Config Mode: The pull-up/pull-down value is latched as PHYADDR[0] at the
de-assertion of reset. See Strapping Options section for details.
21
RXD2 /
Ipd/O
MII Mode:
MII Receive Data Output[2](2) /
PHYAD1
Config Mode: The pull-up/pull-down value is latched as PHYADDR[1] at the
de-assertion of reset. See Strapping Options section for details.
22
RXD1 /
Ipd/O
MII Mode:
MII Receive Data Output[1](2) /
PHYAD2
Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See Strapping Options section for details.
23
RXD0 /
Ipu/O
MII Mode:
MII Receive Data Output[0](2) /
DUPLEX
Config Mode: The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset. See Strapping Options section for details.
24
GND
Gnd
Ground
25
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD
July 2010
9
M9999-071210-1.0
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