LC6513A(2001) View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC6513A
(Rev.:2001)

Single-Chip 4-Bit Microcomputer for Control-Oriented Applications (Low-Threshold Input, On-Chip FLT Driver)

SANYO -> Panasonic 

LC6512A, LC6513A

Continued from preceding page.

Pin Name

PB0-3

PC0-3

PD0-3

PE0-3

PF0-3

PG0-3

PH0-3

Pl0, 1

Input/Output

Input

Input/Output

Input/Output

Output

Output

Output

Output

Output

Function

Input port B0 to B3 (Normal voltage)

Capable of 4-bit input and single-bit decision for branch

Input/output common port C0 to C3 (Normal voltage)

Capable of 4-bit input and single-bit decision for branch during input

Capable of 4-bit output and single-bit set/reset during output

Input/output common port D0 to D3 (Normal voltage)

Capable of 4-bit input and single-bit decision for branch during input

Capable of 4-bit output and single-bit set/reset during output

Output port E0 to E3 (Digit driver output)

Capable of 4-bit output and single-bit set/reset

Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch

Output port F0 to F3 (Digit driver output)

Capable of 4-bit output and single-bit set/reset

Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch

Output port G0 to G3 (Segment driver output)

Capable of 4-bit output and single-bit set/reset

Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch

Output port H0 to H3 (Segment driver output)

Capable of 4-bit output and single-bit set/reset

Capable of 4-bit input of output latch contents and single-bit decision of output latch for branch

Output port I0, I1 (Digit driver output)

Capable of 2-bit output and single-bit set/reset

Capable of 2-bit input of output latch contents and single-bit decision of output latch for branch

0SC1

0SC2

VDD

VSS

TEST

Input

Output

Input

Input

A ceramic resonator is connected to this pin and pin OSC2 in the internal clock mode.

Pin for externally connecting a resonance circuit for the internal clock mode

Power supply pin

Normally connected to +5V

Connected to 0V power supply

IC test pin

Normally connected to VSS(0V)

Specifications

Absolute Maximum Ratings at Ta = 25˚C, VSS=0V

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

Input voltage

Output voltage

Peak output current

Allowable power dissipation

Operating temperature

Storage temperature

VDD max

VIN

VOUT(1)

VOUT(2)

IO(1)

IO(2)

IO(3)

IO(4)

Pd max(1)

Pd max(2)

Topr

Tstg

lnput pins other than OSC1

Ports C,D OSC2

Ports E,F,G,H,I

Ports C,D:Each pin

Ports E,F,I:Each pin

Ports G, H:Each pin

All pins of ports C to I

Ta=–30 to +70°C (Flat package)

Ta=–30 to +70°C (DIP)

–0.3 to +7.0 V

–0.3 to VDD+0.3 (Note1) V

–0.3 to VDD+0.3 V

VDD–45 to VDD+0.3 V

–2.0 to +2.0 mA

–15 to 0 mA

–10 to 0 mA

–90 to +16 mA

350 mW

600 mW

–30 to +70 ˚C

–55 to +125 ˚C

(Note1) For pin OSCl, up to oscillation amplitude generated when internally oscillated under the recommended

oscillation conditions in Fig. 2 is allowable.

[Note] When mounting the QIP package version on the board, do not dip it in solder.

No.2367–4/24

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