LC7185-8750(1998) View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC7185-8750
(Rev.:1998)

CB Transceiver PLL Frequency Synthesizer and Controller

SANYO -> Panasonic 

(3) Timing Requirements for Hold Mode

pin

pin

LC7185-8750

Normal mode

Hold mode

Normal mode

VDD must remain at 5.0 V or higher (crystal oscillator requirement) for 6.0 ms (t HOLD) after the HOLD line is asserted (HOLD

= 0 (< 0.3 VDD). After this, VDD may go as low as 3.2 V.

There are no constraints on timing for the HOLD and VDD pins when the chip is leaving hold mode.

The signal can be activated in one of two orders.

If HOLD is already deactivated (> 0.7 VDD), the LC7185-8750 leaves hold mode within 2.0 ms after VDD rises to >5.0 V.

If VDD is > 5.0 V, the LC7185-8750 enters normal mode within 2.0 ms after HOLD is deactivated.

(4) Reset Timing

1. Reset timing (e.g. battery replacement)

pin

pin

Note: tINIT should be greater than 1.0 µs.

2. Reset caused by a sudden voltage (VDD) drop

pin

pin

If VDD drops momentarily down to less than 3.2 V and rises up to more than 5.0 V t > tINIT (t > 1.0 µs), a reset may be

generated.

No. 3356-10/12

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