LC72714 View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC72714 Datasheet PDF : 29 Pages
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LC72714W
Layer 4 CRC Register
Address Register R/W Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
06H
CRC4
W
00H
(LSB)
This is the data group write register used for the layer 4 CRC check. It is used only when the parallel interface is used.
Applications should specify the dedicated CCB address when using the serial interface.
Status Register
Address Register R/W Initial value
01H
STAT
R
—
*: BIT0 is unused.
BIT7
VH
BIT6
BLK
BIT5
FRM
BIT4
ERR
BIT3
PRI
BIT2
HEAD
BIT1
CRC4
BIT0
*
• VH
0: Indicates data for which only horizontal correction was performed.
1: Indicates data for which after horizontal correction, vertical and then second horizontal correction were performed as
well.
• BLK
0: Indicates data that was received with block synchronization unsynchronized.
1: Indicates data that was received with block synchronization synchronized.
• FRM
0: Indicates data that was received with frame synchronization unsynchronized.
1: Indicates data that was received with frame synchronization synchronized.
• ERR
0: Indicates data for which error correction completed and no errors were detected in the level 2 CRC check.
1: Indicates data for which error correction was not possible or for which errors were detected in the level 2 CRC
check.
• PRI
0: Indicates data that was inferred to be data block data by the frame synchronization circuit.
1: Indicates data that was inferred to be parity block data by the frame synchronization circuit.
• HEAD
0:
1: Indicates data that was inferred to be in the frame head block by the frame synchronization circuit.
This flag is valid only when VH is 0.
• CRC4
0: Indicates that the layer 4 CRC detection circuit division registers were not all zeros.
1: Indicates that the layer 4 CRC detection circuit division registers were all zeros, i.e. that there were no errors.
The result at the point immediately prior to register readout is loaded into this flag.
Block Number Register
Address Register R/W Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
02H BLNO
R
—
BLN7
BLN6
BLN5
BLN4
BLN3
BLN2
BLN1
BLN0
Indicates the block number or the parity block number of the output data.
A single frame consists of data blocks numbered 0 to 189 and parity blocks numbered 0 to 81. Output following vertical
correction does not include parity block data.
The value of the block number register is undefined if VEC_HALT (bit 2 in control register 1) is set to 1.
No. 6871-10/29
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