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LC75700T View Datasheet(PDF) - SANYO -> Panasonic

Part Name
Description
Manufacturer
LC75700T
SANYO
SANYO -> Panasonic SANYO
LC75700T Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC75700T
Pin Functions
Pin
Pin No.
Function
Active I/O Handling when unused
KI1 to KI5
1 to 5 Key scan inputs. These pins have built-in pull-down resistors.
H
I
GND
KS1 to KS3
Key scan outputs. Although normal key scan timing lines require diodes to be
inserted in the timing lines to prevent shorts, since these outputs are unbalanced
6 to 8 CMOS transistor outputs, these outputs will not be damaged by shorting when
0
these outputs are used to from a key matrix.
Open
Key scan outputs and general-purpose output ports shared-function pins.
KS4/P4 to KS6/P2 9 to 11 These pins can be set the key scan output ports or the general-purpose output
0
ports by the control data “KP1 and KP2”.
P1
12 The P1 is general-purpose output ports.
0
Open
Open
Oscillator connection. An oscillator circuit is formed by connecting an external
OSC
14 resistor and capacitor at this pin.
— I/O
VDD
RES
CE
CL
DI
DO
Reset input. that re-initializes the LSI internal states. This pin must be used.
• When RES is low (VSS)
— Key scanning disabled: KS1 to KS3 = low (VSS).
— Key scan outputs and general output ports shared-function pins:
KS4/P4 to KS6/P2 = low (VSS).
16
— General-purpose output port: P1 = low (VSS).
— All the key data is reset to low.
• When RES is high (VDD)
— The states of the pins as key scan output pins or general-purpose output
ports, must be set with the control data.
— And key scanning is a enabled.
Note that serial data must be transferred when RES is high.
18 Serial data interface. Connections to the controller. Note that DO, being
an open-drain output, requires a pull-up resistor.
19
CE: Chip enable
20
CL: Synchronization clock
DI: Transfer data
17
DO: Output data
L
I
H
I
v
I
I
O
GND
GND
Open
VDD
15 Power supply. A voltage of between 2.7 V and 5.5 V must be supplied.
VSS
13 Ground. Must be connected to the system ground.
No. 7632-6/16

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