LC75808W(2010) View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC75808W Datasheet PDF : 38 Pages
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LC75808W
2. LC75808W internal block states during the system reset
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined
after the SP control data bit is transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state.
• CONTRAST ADJUSTER
Reset is applied and operation of the display contrast adjustment circuit is disabled. After that, once CT0 to CT3
and CTC in the control data have been transferred to the IC it will then be possible to set the display contrast.
• KEY SCAN, KEY BUFFER
Reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the key
data is all set to 0. After that, once KC1 to KC6 in the control data have been transferred to the IC it will then be
possible to perform key scan operations.
• GENERAL PORT
Reset is applied and the states of the general-purpose output ports are held fixed at the low level (VSS).
• CCB INTERFACE, SHIFT REGISTER, CONTROL REGISTER
Since serial data transfer is possible, these circuits are not reset.
VLCD
VLCD0
VLCD1
VLCD2
VLCD3
VLCD4
VDD
VSS
TEST
GENERAL
PORT
COMMON
DRIVER
CONTRAST
ADJUSTER
VDET
CLOCK
GENERATOR
SEGMENT DRIVER & LATCH
CONTROL
REGISTER
SHIFT REGISTER
CCB INTERFACE
KEY BUFFER
KEY SCAN
Blocks that are reset
A12921
3. Output pin states during the system reset
Output pin
State during reset
S1 to S60
L(VLCD4)
COM1 to COM10
L(VLCD4)
KS1 to KS6
L(VSS)
P1 to P4
L(VSS)
DO
H *5
Note: *5. Since this output pin is an open-drain output, a pull-up resistor of between 1kΩ and 10 kΩ is required.
This pin is held at the high level even if a key data read operation is performed before the KC1 to KC6
control data has been transferred to the IC.
No.6370-29/38
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