LC75808W(2010) View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC75808W
(Rev.:2010)

1/8 to 1/10 Duty LCD Display Driver with Key Input Function

SANYO -> Panasonic 

LC75808W

Specifications

Absolute Maximum Ratings at Ta = 25°C, VSS = 0V

Parameter

Maximum supply voltage

Input voltage

Output voltage

Output current

Allowable power dissipation

Operating temperature

Symbol

VDD max

VLCD max

VIN1

VIN2

VIN3

VOUT1

VOUT2

VOUT3

IOUT1

IOUT2

IOUT3

IOUT4

Pd max

Topr

Conditions

VDD

VLCD

CE, CL, DI, INH

OSC, KI1 to KI5, TEST

VLCD1, VLCD2, VLCD3, VLCD4

DO

OSC, KS1 to KS6, P1 to P4

VLCD0, S1 to S60, COM1 to COM10

S1 to S60

COM1 to COM10

KS1 to KS6

P1 to P4

Ta=85°C

Storage temperature

Tstg

Ratings

Unit

-0.3 to +7.0

V

-0.3 to +12.0

-0.3 to +7.0

-0.3 to VDD+0.3

V

-0.3 to VLCD+0.3

-0.3 to +7.0

-0.3 to VDD+0.3

V

-0.3 to VLCD+0.3

300

μA

3

1

mA

5

200

mW

-40 to +85

°C

-55 to +125

°C

Allowable Operating Ranges at Ta = -40 to +85°C, VSS = 0V

Parameter

Symbol

Conditions

Ratings

unit

min

typ

max

Supply voltage

VDD

VDD

4.5

6.0

VLCD

VLCD, When the display contrast adjustment

7.0

circuit is used

11.0

V

VLCD

VLCD , When the display contrast adjustment

4.5

11.0

circuit is not used

Output voltage

VLCD0

VLCD0

VLCD4

+4.5

VLCD

V

Input voltage

VLCD1

VLCD2

VLCD3

Input high level voltage

Input low level voltage

Recommended external resistance

VLCD4

VIH1

VIH2

VIL

ROSC

VLCD1

VLCD2

VLCD3

VLCD4

CE, CL, DI, INH

KI1 to KI5

CE, CL, DI, INH, KI1 to KI5

OSC

3/4(VLCD0

-VLCD4)

VLCD0

2/4(VLCD0

-VLCD4)

VLCD0

V

1/4(VLCD0

-VLCD4)

VLCD0

0

1.5

0.8VDD

0.6VDD

0

6.0

V

VDD

V

0.2VDD

V

43

kΩ

Recommended external

capacitance

COSC

OSC

680

pF

Guaranteed oscillation range

fOSC

OSC

25

50

100 kHz

Data setup time

tds

CL, DI

[Figure 2]

160

ns

Data hold time

tdh

CL, DI

[Figure 2]

160

ns

CE wait time

tcp

CE, CL

[Figure 2]

160

ns

CE setup time

tcs

CE, CL

[Figure 2]

160

ns

CE hold time

tch

CE, CL

[Figure 2]

160

ns

High level clock pulse width

tφH

CL

[Figure 2]

160

ns

Low level clock pulse width

tφL

CL

[Figure 2]

160

ns

DO output delay time

tdc

DO RPU=4.7kΩ, CL=10pF *1

[Figure 2]

1.5

μs

DO rise time

tdr

DO RPU=4.7kΩ, CL=10pF *1

[Figure 2]

1.5

μs

Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the

load capacitance CL.

No.6370-2/38

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