LC75010W View Datasheet(PDF) - SANYO -> Panasonic

Part Name

Description

Manufacturer

LC75010W

LC75010W Car Audio DSP

SANYO -> Panasonic 

Pin Functions

Pin No.

97

94

77

80

89

85

92

82

93

81

Pin name

AINRP1

AINRN1

AINLP1

AINLN1

AINRP2

AINLP2

AINRP3

AINLP3

AINRP4

AINLP4

34

PWDB

35

RSTB

40

INTB

10

TEST0

11

TEST1

12

TEST2

13

TEST3

14

TEST4

17

TEST5

18

TEST6

19

TEST7

20

TEST8

21

TEST9

22

TEST10

41

TEST11

44

TEST12

45

TEST13

46

TEST14

49

XIN

50

XOUT

27

VCO

28

PDO

36

CE

37

CL

38

DI

39

DO

33

BUSY

74

VFLO

73

VFLI

71

VFRO

70

VFRI

58

VRLO

59

VRLI

55

VRRO

56

VRRI

LC75010W

Input/Output (I/O)

I

I

I

I

I

I

I

I

I

I

I

I

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

O

I

O

I

I

I

O

O

O

I

O

I

O

I

O

I

Function

Analog BTL input (Rch +)

Analog BTL input (Rch -)

Analog BTL input (Lch +)

Analog BTL input (Lch -)

Analog OTL input1 (Rch +)

Analog OTL input1 (Lch +)

Analog OTL input2 (Rch +)

Analog OTL input2 (Lch +)

Analog OTL input3 (Rch +)

Analog OTL input3 (Lch +)

Standby mode (active low)

Setting the PWDB pin to the low level sets the LC75010W to standby mode (also know as "power

down mode").

In standby mode, the DSP system clock and the crystal oscillator are stopped and the whole

LC75010W goes to the stopped state. This pin must be held at the high level during normal

operation.

Reset (active low)

A reset is normally applied at power on, after recovering from a temporary power outage, and after

returning from standby mode ("power down mode").

Interrupt (active low) (Software clip input (0/1))

Provides feedback control to the DSP to prevent clipping when an overflow occurs in the amplifier

output.

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Test pin

Crystal input (384 fs = 16.9344 MHz) (fs = 44.1 kHz)

Crystal output

VCO control

Charge pump output

CCB enable

CCB clock

Data in

Data out

CCB ready monitor

Outputs the state of the DSP CCB receive buffer.

A low-level output from the BUSY pin indicates that the buffer is empty.

A high-level output indicates that command data is present in the receive buffer.

Volume front Lch output

Volume front Lch input

Volume front Rch output

Volume front Rch input

Volume rear Lch output

Volume rear Lch input

Volume rear Rch output

Volume rear Rch input

Continued on next page.

No. N7349-5/12

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