LC75010W View Datasheet(PDF) - SANYO -> Panasonic
Part Name
Description
Manufacturer
LC75010W Datasheet PDF : 12 Pages
| |||
• Serial Data Timing
CL: Normally high
CE
tCH
CL
VIH
VIL
VIH
DI
VIL
tSU
DO
LC75010W
VIH
tCL
VIH
VIL
VIH
tEL
tES
tHD VIL
tDC
Internal
data latch
CL: Normally low
When CL is stopped at the high level
CE
tCH
tCL
CL
VIH
VIL
VIH
VIH
DI
VIL
tSU
tHD VIL
DO
VIH
VIL
VIH
VIL
tEL
tES
tDC
tDC
Internal
data latch
When CL is stopped at the low level
VIL
VIH
tEH
tDH
tLC
Old New
VIL
VIH
tEH
tDH
tLC
Old New
Reset Timing
After power has been applied, and after crystal oscillator operation and PLL circuit operation have stabilized, a reset must
be applied at the point that the Vref voltages (Vref1, Vref2, and Vref3) exceed the minimum level of 2.35 V. The reset
period must be set up to include a period of at least 0.5 µs during which the reset signal is held fixed at the low level.
Audio processing (audio input/audio output) cannot be performed during the A/D converter calibration period (100 ms),
which directly follows the reset.
Note on Changes to the DSP Core Main Clock
The LC75010W DSP core main clock can be switched by setting the TEST8 pin either low or high as shown below.
TEST8
DSP core main clock (Crystal oscillator: 16.9344 MHz)
Low (DVSS)
High (DVDD 3.3)
38.1024 MHz
40.2192 MHz
No. N7349-9/12
Share Link: 