LH28F008SCL-12 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SCL-12

Flash Memory 8M (1M ×8)

Sharp Electronics 

SHARP

LHF08CH3

8

3 BUS OPERATION

The local CPU reads and writes flash memory

in-system. All bus cycles to or from the flash memory

conform to standard microprocessor bus cycles.

3.1 Read

Information can be read from any block, identifier

codes, or status register independent of the V,,

voltage. RP# can be at either V,, or V,,.

The first task is to write the appropriate read mode

command (Read Array, Read Identifier Codes, or

Read Status Register) to the CUI. Upon initial device

power-up or after exit from deep power-down mode,

the device automatically resets to read array mode.

Four control pins dictate the data flow in and out of

the component: CE#, OE#, WE#, and RP#. CE# and

OE# must be driven active to obtain data at the

outputs. CE# is the device selection control, and

when active enables the selected memory device.

OE# is the data output (DQ,-DQ,) control and when

active drives the selected memory data onto the I/O

bus. WE# must be at V,, and RP# must be at V,, or

V,,. Figure 15 illustrates a read cycle.

3.2 Output Disable

JVith OE# at a logic-high level (V,,), the device

outputs are disabled. Output pins DC+,-DQ, are

olaced in a high-impedance state.

3.3 Standby

ZE# at a logic-high level (VI,) places the device in

standby mode #which substantially reduces device

lower consumption. DQc-DQ, outputs are placed in

I high-impedance state independent of OE#. If

deselected during block erase, byte write, or lock-bit

:onfiguration, the device continues functioning, and

consuming

completes.

active power until the operatior

3.4 Deep Power-Down

RP# at V,, initiates the deep power-down mode.

In read modes, RP#-low deselects the memory

places output drivers in a high-impedance state ant

turns off all internal circuits. RP# must be held low fo

a minimum of 100 ns. Time tPHQv is required afte

return from power-down until initial memory acces:

outputs are valid. After this wake-up interval, norma

operation is restored. The CUI is reset to read array

mode and status register is set to 80H.

During block erase, ,“;~low~ritell

configuration modes,

o;bo~ck;+;

operation. RY/BY# remains low until the rese

operation is complete. Memory contents beins

altered are no longer valid; the data may be partially

erased or written. Time tPHwL is requirod after RPB

goes to logic-high (V,,) before another command car

be written.

As with any automated device, it is important tc

assert RP# during system reset. When the systen-

comes out of reset, it expects to read from the flask

memory. Automated flash memories provide status

information when accessed during block erase, byte

write, or lock-bit configuration modes. If a CPU resei

occurs with no flash memory reset, proper CPU

initialization may not occur because the flash memory

may be providing status information instead of array

data. SHARP’s flash memories allow proper CPU

initialization following a system reset through the use

of the RP# input. In this application, RP# is controlled

by the same RESET# signal that resets the system

CPU.

Rev. 1.0

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