LH28F008SCL-12 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F008SCL-12

Flash Memory 8M (1M ×8)

Sharp Electronics 

SHARP

LHF08CH3

7

2 PRINCIPLES OF OPERATION

The LH28F008SCT-L12 SmartVoltage Flash memory

includes an on-chip WSM to manage block erase,

byte write, and lock-bit configuration functions. It

allows for: 100% TTL-level control inputs, fixed power

supplies during block erasure, byte write, and lock-bit

configuration, and minimal processor overhead with

RAM-Like interface timings.

After initial device power-up or return from deep

power-down mode (see Bus Operations), the device

defaults to read array mode. Manipulation of external

memory control pins allow array read, standby, and

output disable operations.

Status register and identifier codes can be accessed

through the CUI independent of the V,, voltage. High

voltage on V,, enables successful block erasure,

byte writing, and lock-bit configuration. All functions

associated with altering memory contents-block

erase, byte write, Lock-bit configuration, status, and

identifier codes-are accessed via the CUI and

verified through the status register.

Commands

are written

using standard

microprocessor write timings. The CUI contents serve

as input to the WSM, which controls the block erase,

byte write, and lock-bit configuration. The internal

algorithms are regulated by the WSM, including pulse

repetition, internal verification, and margining of data.

Addresses and data are internally latch during write

cycles. Writing the appropriate command outputs

array data, accesses the identifier codes, or outputs

status register data.

Interface software that initiates and polls progress of

block erase, byte write, and lock-bit configuration can

be stored in any block. This code is copied to and

executed from system RAM during flash memory

updates. After successful completion, reads are

again possible via the Read Array command. Block

erase suspend allows system software to suspend a

block erase to read or write data from any other

block. Byte write suspend allows system software to

suspend a byte write to read data from any other

flash memory array location.

FFFFF

FOOOO

EFFFF

EOOW

DFFFF

DO000

CFFFF

coooo

BFFFF

BOO00

AFFFF

AOOW

SFFFF

90000

8FFFF

80000

7FFFF

70000

6FFFF

60000

SFFFF

50000

4FFFF

40000

JFFFF

30000

PFFFF

20000

1 FFFF

10000

OFFFF

FigUre 3. Memory

Map

2: 1 Data Protection

Depending on the application, the system designer

may choose to make the V,, power supply

switchable (available only when memory block

erases, byte writes, or lock-bit configurations are

required) or hardwired to V,,,,,z13. The device

accommodates

either design practice and

encourages optimization of the processor-memory

interface.

When Vpp~VppLK, memory contents cannot be

altered. The CUI, with two-step block erase, byte

write, or lock-bit configuration command sequences,

provides protection from unwanted operations even

when high voltage is applied to V,,. All write

functions are disabled when Vcc is below the write

lockout voltage VLKO or when RP# is at V,,. The

device’s block locking capability provides additional

protection from inadvertent code or data alteration by

gating erase and byte write operations.

Rev.1.3

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