LH28F800BJHE-PBTL90 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

Manufacturer

LH28F800BJHE-PBTL90

8M (x8/x16) Flash Memory

Sharp Electronics 

LHF80J05

28

5.6 Power-Up/Down Protection

The device is designed to offer protection against

accidental block erase, full chip erase, word/byte write or

lock-bit configuration during power transitions. Upon

power-up, the device is indifferent as to which power

supply (VCCW or VCC) powers-up first. Internal circuitry

resets the CUI to read array mode at power-up.

A system designer must guard against spurious writes for

VCC voltages above VLKO when VCCW is active. Since

both WE# and CE# must be low for a command write,

driving either to VIH will inhibit writes. The CUI’s two-

step command sequence architecture provides added level

of protection against data alteration.

In-system block lock and unlock capability prevents

inadvertent data alteration. The device is disabled while

RP#=VIL regardless of its control inputs state.

5.7 Power Dissipation

When designing portable systems, designers must consider

battery power consumption not only during device

operation, but also for data retention during system idle

time. Flash memory’s nonvolatility increases usable

battery life because data is retained when system power is

removed.

5.8 Data Protection Method

Noises having a level exceeding the limit specified in the

specification may be generated under specific operating

conditions on some systems. Such noises, when induced

onto WE# signal or power supply, may be interpreted as

false commands, causing undesired memory updating. To

protect the data stored in the flash memory against

unwanted overwriting, systems operating with the flash

memory should have the following write protect designs,

as appropriate:

1) Protecting data in specific block

When a lock bit is set, the corresponding block (includes

the 2 boot blocks) is protected against overwriting. By

setting a WP# to low, only the 2 boot blocks can be

protected against overwriting. By using this feature, the

flash memory space can be divided into the program

section (locked section) and data section (unlocked

section). The permanent lock bit can be used to prevent

false block bit setting. For further information on

setting/resetting lock-bit, refer to the specification. (See

chapter 4.10 and 4.11.)

2) Data protection through VCCW

When the level of VCCW is lower than VCCWLK (lockout

voltage), write operation on the flash memory is disabled.

All blocks are locked and the data in the blocks are

completely write protected. For the lockout voltage, refer

to the specification. (See chapter 6.2.3.)

3) Data protection through RP#

When the RP# is kept low during read mode, the flash

memory will be reset mode, then write protecting all

blocks. When the RP# is kept low during power up and

power down sequence such as voltage transition, write

operation on the flash memory is disabled, write

protecting all blocks. For the details of RP# control, refer

to the specification. (See chapter 5.6 and 6.2.7.)

Rev. 1.27

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