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LH79524 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
Manufacturer
LH79524
NXP
NXP Semiconductors. NXP
LH79524 Datasheet PDF : 62 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LH79524/LH79525
NXP Semiconductors
System-on-Chip
Table 2. LH79524 Pin Descriptions (Cont’d)
LFBGA
PIN
SIGNAL NAME
TYPE
DESCRIPTION
K14 nOE
J16 nWE
A16 USBDN
O Static Memory Output Enable
O Static Memory Write Enable
I/O USB Data Negative (Differential Pair output, single ended and Differential pair input)
A15 USBDP
I/O USB Data Positive (Differential Pair output, single ended and Differential pair input)
E2 AN0/UL/X+
I ADC Input 0, 4-wire touch screen Upper Left, 5-wire touch screen X+
F2 AN1/UR/X–
I ADC Input 1, 4-wire touch screen Upper Right, 5-wire touch screen X–
G2 AN2/LL/Y+/PJ3
I
ADC Input 2, 4-wire touch screen Lower Left, 5-wire touch screen Y+; multiplexed
with GPIO Port J3 (input only)
H2 AN3/LR/Y–/PJ0
I
ADC Input 3, 4-wire touch screen Upper Right, 5-wire touch screen Y–;
multiplexed with GPIO Port J0 (input only)
H3 AN4/WIPER/PJ1
I
ADC Input 4, 5-wire touch screen Wiper input; multiplexed with GPIO Port J1
(input only)
F1 AN5/PJ5/INT5
I ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
F3 AN6/PJ7/INT7
I ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
E1 AN7/PJ6/INT6
I ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
G3 AN8/PJ4
I ADC Input 8; multiplexed with GPIO Port J4 (input only)
G1 AN9/PJ2
I ADC Input 9; multiplexed with GPIO Port J2 (input only)
J3 CTCLK/INT4/BATCNTL I/O Timer[2:0] External Clock input; muxed with External Int 4 and Battery Control
N1
PA0/INT2/UARTRX2/
UARTIRRX2
I/O
General Purpose I/O Signal — Port A0; multiplexed with UART2 Received Serial
Data Input, UART2 Infrared Received Serial Data In, and External Interrupt 2
M2
PA1/INT3/UARTTX2/
UARTIRTX2
I/O
General Purpose I/O Signal — Port A1; multiplexed with UART2 Transmitted
Serial Data Output, UART2 Serial Transmit Data Out, and External Interrupt 3
L3
PA2/CTCAP0A/
CTCMP0A
I/O
General Purpose I/O Signal — Port A2; multiplexed with Counter/Timer 0
Capture A input and Counter/Timer 0 Compare A output
M1
PA3/CTCAP0B/
CTCMP0B
I/O
General Purpose I/O Signal — Port A3; multiplexed with Counter/Timer 0
Capture B input and Counter/Timer 0 Compare B output
L2
PA4/CTCAP1A/
CTCMP1A
I/O
General Purpose I/O Signal — Port A4; multiplexed with Counter/Timer 1
Capture A input and Counter/Timer 1 Compare A output
L1
PA5/CTCAP1B/
CTCMP1B
I/O
General Purpose I/O Signal — Port A5; multiplexed with Counter/Timer 1
Capture B input and Counter/Timer 1 Compare B output
K3
PA6/CTCAP2A/
CTCMP2A/SDA
I/O
General Purpose I/O Signal — Port A6; multiplexed with Counter/Timer 2
Capture A input, Counter/Timer 2 Compare A output, I2C Bus Data (open drain)
K2
PA7/CTCAP2B/
CTCMP2B/SCL
I/O
General Purpose I/O Signal — Port A7; multiplexed with Counter/Timer 2
Capture B input, Counter/Timer 2 Compare B output, I2C Bus Clock (open drain)
R2
PB0/nDACK/
nUARTCTS0
I/O
General Purpose I/O Signal — Port B0; multiplexed with DMA Acknowledge and
UART0 CTS
R1
PB1/DREQ/
nUARTRTS0
I/O
General Purpose I/O Signal — Port B1; multiplexed with DMA Request and
UART0 RTS
P2 PB2/SSPFRM/I2SWS
N3 PB3/SSPCLK/I2SCLK
I/O
General Purpose I/O Signal — Port B2; multiplexed with SSP Serial Frame Output
and I2S Frame Output
I/O General Purpose I/O Signal — Port B3; multiplexed with SSP Clock and I2S Clock
PB4/SSPRX/I2SRXD/
M4 UARTRX1/
UARTIRRX1
I/O
General Purpose I/O Signal — Port B4; multiplexed with SSP Data In, I2S Data In,
UART1 Serial Data In, and UART1 Infrared Data In
P1
PB5/SSPTX/I2STXD/
UARTTX1/UARTIRTX1
I/O
General Purpose I/O Signal — Port B5; multiplexed with SSP Data Out, I2S Data
Out, UART1 Data Out, and UART1 IR Data Out
N2
PB6/INT0/UARTRX0/
UARTIRRX0
I/O
General Purpose I/O Signal — Port B6; multiplexed with UART0 Infrared Received
Serial Data Input, UART0 Received Serial Data In, and External Interrupt 0
6
Rev. 02 17 March 2009
Product data sheet

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