LPC1102UK(2011) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC1102UK
(Rev.:2011)

32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

NXP Semiconductors. 

NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

11. Application information

11.1 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy

environment beyond the ADC specifications listed in Table 6:

• The ADC input trace must be short and as close as possible to the LPC1102 chip.

• The ADC input traces must be shielded from fast switching digital signals and noisy

power supply lines.

• Because the ADC and the digital core share the same power supply, the power supply

line must be adequately filtered.

• To improve the ADC performance in a very noisy environment, put the device in Sleep

mode during the ADC conversion.

11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a

clock in slave mode, it is recommended that the input be coupled through a capacitor with

Ci = 100 pF. To limit the input voltage to the specified range, choose an additional

capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave

mode, a minimum of 200 mV (RMS) is needed.

LPC1xxx

XTALIN

Ci

Cg

100 pF

002aae788

Fig 19. Slave mode operation of the on-chip oscillator

In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF

(Figure 19), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This

corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.

11.3 Standard I/O pad configuration

Figure 20 shows the possible pin modes for standard I/O pins with analog input function:

• Digital output driver

• Digital input: Pull-up enabled/disabled

• Digital input: Pull-down enabled/disabled

• Digital input: Repeater mode enabled/disabled

• Analog input

LPC1102

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 24 June 2011

© NXP B.V. 2011. All rights reserved.

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