LPC2114 View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
LPC2114
Philips Electronics
LPC2114 Datasheet PDF : 34 Pages
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Philips Semiconductors
LPC2114/LPC2124
Single-chip 16/32-bit microcontrollers
6. Functional description
Details of the LPC2114/LPC2124 systems and peripheral functions are described in
the following sections.
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM® architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler than those of microprogrammed
Complex Instruction Set Computers. This simplicity results in a high instruction
throughput and impressive real-time interrupt response from a small and
cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed,
its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb
code operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
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Product data
6.2 On-Chip Flash program memory
The LPC2114/LPC2124 incorporate a 128 kB and 256 kB Flash memory system
respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase
and/or program the Flash while the application is running, allowing a great degree of
flexibility for data storage field firmware upgrades, etc. When on-chip bootloader is
used, 120/248 kB of Flash memory is available for user code.
The LPC2114/LPC2124 Flash memory provides a minimum of 100,000 erase/write
cycles and 20 years of data retention.
On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the
LPC2114/LPC2124 on-chip Flash memory. When the CRP is enabled, the JTAG
debug port and ISP commands accessing either the on-chip RAM or Flash memory
Rev. 03 — 22 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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