LPC2109 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC2109

Single-chip 16/32-bit microcontrollers; 64/128/256 kB ISP/IAP flash with 10-bit ADC and CAN

NXP Semiconductors. 

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

6.18.2 PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled

Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the

multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper

frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so

there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and

bypassed following a chip Reset and may be enabled by software. The program must

configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a

clock source. The PLL settling time is 100 µs.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2109/2119/2129: the RESET pin and Watchdog Reset.

The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of

chip Reset by any source starts the Wake-up Timer (see Wake-up Timer description

below), causing the internal chip reset to remain asserted until the external Reset is

de-asserted, the oscillator is running, a fixed number of clocks have passed, and the

on-chip flash controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is the Reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of Reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the Wake-up Timer.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufficient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2109/2119/2129 allows the user to enable different levels of

security in the system so that access to the on-chip flash and use of the JTAG and ISP

can be restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection.

LPC2109_2119_2129_6

Product data sheet

Rev. 06 — 10 December 2007

© NXP B.V. 2007. All rights reserved.

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