LPC2212 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC2212

16/32-bit ARM microcontrollers; 128/256 kB ISP/IAP flash with 10-bit ADC and external memory interface

NXP Semiconductors. 

NXP Semiconductors

LPC2212/2214

16/32-bit ARM microcontrollers

6.11 I2C-bus serial I/O controller

The I2C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock

line (SCL), and a serial data line (SDA). Each device is recognized by a unique address

and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with

the capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus; it can be

controlled by more than one bus master connected to it.

The I2C-bus implemented in LPC2212/2214 supports a bit rate up to 400 kbit/s (Fast

I2C-bus).

6.11.1 Features

• Standard I2C-bus compliant interface.

• Easy to configure as Master, Slave, or Master/Slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus may be used for test and diagnostic purposes.

6.12 SPI serial I/O controller

The LPC2212/2214 each contain two SPIs. The SPI is a full duplex serial interface,

designed to be able to handle multiple masters and slaves connected to a given bus. Only

a single master and a single slave can communicate on the interface during a given data

transfer. During a data transfer the master always sends a byte of data to the slave, and

the slave always sends a byte of data to the master.

6.12.1 Features

• Compliant with Serial Peripheral Interface (SPI) specification.

• Synchronous, Serial, Full Duplex communication.

• Combined SPI master and slave.

• Maximum data bit rate of 1⁄8 of the input clock rate.

6.12.2 Features available in LPC2212/2214/01 only

LPC2212_2214_4

Product data sheet

• Eight to 16 bits per frame.

Rev. 04 — 3 January 2008

© NXP B.V. 2008. All rights reserved.

18 of 45

Share Link: