LPC1788(2011) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC1788
(Rev.:2011)

32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC

NXP Semiconductors. 

NXP Semiconductors

LPC178x/7x

32-bit ARM Cortex-M3 microcontroller

 Cortex-M3 system tick timer, including an external clock input option.

 Standard JTAG test/debug interface as well as Serial Wire Debug and Serial

WireTrace Port options.

 Emulation trace module supports real-time trace.

 Boundary scan for simplified board testing.

 Non-maskable Interrupt (NMI) input.

 Memory:

 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. The combination of an enhanced

flash memory accelerator and location of the flash memory on the CPU local

code/data bus provides high code performance from flash.

 96 kB on-chip SRAM includes:

64 kB of SRAM on the CPU with local code/data bus for high-performance CPU

access.

Two 16 kB SRAM blocks with separate access paths for higher throughput. These

SRAM blocks may be used for DMA memory as well as for general purpose

instruction and data storage.

 4032 byte on-chip EEPROM.

 LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film

Transistors (TFT) displays.

 Dedicated DMA controller.

 Selectable display resolution (up to 1024  768 pixels).

 Supports up to 24-bit true-color mode.

 External Memory Controller (EMC) provides support for asynchronous static memory

devices such as RAM, ROM and flash, as well as dynamic memories such as single

data rate SDRAM.

 Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and

Digital-to-Analog converter peripherals, timer match signals, GPIO, and for

memory-to-memory transfers.

 Serial interfaces:

 Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

 USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and

associated DMA controller.

 Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and

RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one

UART (USART4) supports IrDA, synchronous mode, and a smart card mode

conforming to ISO7816-3.

 Three SSP controllers with FIFO and multi-protocol capabilities. The SSP

interfaces can be used with the GPDMA controller.

 Three enhanced I2C-bus interfaces, one with a true open-drain output supporting

the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two

with standard port pins. Enhancements include multiple address recognition and

monitor mode.

 I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

LPC178X_7X

Objective data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 27 May 2011

© NXP B.V. 2011. All rights reserved.

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