LPC47M182 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
Manufacturer
LPC47M182 Datasheet PDF : 223 Pages
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Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table Of Contents
Chapter 1 General Description ........................................................................................................... 11
Chapter 2 Pin Layout........................................................................................................................... 12
Chapter 3 Description of Pin Functions ............................................................................................. 14
3.1 Buffer Name Descriptions ................................................................................................................. 23
3.2 Pins With Internal Resistors .............................................................................................................. 23
3.3 Pins That Require External Resistors ............................................................................................... 24
3.4 Default State of Pins.......................................................................................................................... 25
Chapter 4 Block Diagram.................................................................................................................... 29
Chapter 5 Power and Clock Functionality......................................................................................... 30
5.1 3 Volt Operation / 5 Volt Tolerance ................................................................................................... 30
5.2 VCC Power........................................................................................................................................ 30
5.3 VTR Power ........................................................................................................................................ 30
5.3.1 Trickle Power Functionality.....................................................................................................................31
5.4 V5P0_STBY Power ........................................................................................................................... 31
5.5 32.768 kHz Trickle Clock Input.......................................................................................................... 31
5.5.1 Indication of 32KHZ Clock ......................................................................................................................31
5.6 14.318 MHz Clock Input .................................................................................................................... 32
5.7 Internal PWRGOOD .......................................................................................................................... 32
5.8 Maximum Current Values.................................................................................................................. 32
5.9 Power Management Events (PME/SCI)............................................................................................ 32
Chapter 6 Functional Description....................................................................................................... 33
6.1 Super I/O Registers........................................................................................................................... 33
6.2 Host Processor Interface (LPC) ........................................................................................................ 34
6.3 LPC Interface .................................................................................................................................... 34
6.3.1 LPC Interface Signal Definition...............................................................................................................34
6.3.2 LPC Cycles .............................................................................................................................................34
6.3.3 Field Definitions ......................................................................................................................................35
6.3.4 NLFRAME Usage ...................................................................................................................................35
6.3.5 I/O Read and Write Cycles .....................................................................................................................35
6.3.6 DMA Read and Write Cycles ..................................................................................................................35
6.3.7 DMA Protocol .........................................................................................................................................35
6.3.8 POWER MANAGEMENT .......................................................................................................................36
6.3.9 SYNC Protocol .......................................................................................................................................36
6.3.10 I/O and DMA START Fields ................................................................................................................37
6.3.11 LPC TRANSFERS ..............................................................................................................................37
6.4 Floppy Disk Controller ....................................................................................................................... 38
6.4.1 FDC Configuration Registers ..................................................................................................................38
6.4.2 FDC Internal Registers ...........................................................................................................................38
6.4.3 STATUS REGISTER A (SRA) ................................................................................................................39
6.4.4 STATUS REGISTER B (SRB) ................................................................................................................40
6.4.5 DIGITAL OUTPUT REGISTER (DOR) ...................................................................................................42
6.4.6 TAPE DRIVE REGISTER (TDR) ............................................................................................................44
6.4.7 DATA RATE SELECT REGISTER (DSR) ..............................................................................................45
6.4.8 MAIN STATUS REGISTER ....................................................................................................................47
6.4.9 DATA REGISTER (FIFO) .......................................................................................................................48
6.4.10 DIGITAL INPUT REGISTER (DIR)......................................................................................................49
6.4.11 CONFIGURATION CONTROL REGISTER (CCR) .............................................................................50
6.4.12 STATUS REGISTER ENCODING ......................................................................................................51
SMSC LPC47M182
3
Revision 1.8 SMSC/Non-SMSC Register Sets (02-24-05)
DATASHEET
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