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LPC47N267(2000) View Datasheet(PDF) - SMSC -> Microchip

Part Name
Description
Manufacturer
LPC47N267
(Rev.:2000)
SMSC
SMSC -> Microchip SMSC
LPC47N267 Datasheet PDF : 180 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
STQFP PIN #
NAME
SYMBOL
52
General
GP14/
Purpose I/O/
IRQ Input 2 IRQIN2
54
General
GP15/
Purpose I/O/
IRQ Input 3 IRQIN3
55
General
GP16/
Purpose I/O/
IRQ Input 4 IRQIN4
64
General
GP23/
Purpose I/O/
Floppy on
FDC_PP
Parallel Port
BUFFER
TYPE PER
FUNCTION1
(I/O8/OD8)/
DESCRIPTION
General Purpose Input/Output.
I
(I/O8/OD8)/
External Interrupt Input. Steerable onto one of the
15 Serial IRQs.
General Purpose Input/Output.
I
(I/O8/OD8)/
External Interrupt Input. Steerable onto one of the
15 Serial IRQs.
General Purpose Input/Output.
I
(I/O8/OD8)/
External Interrupt Input. Steerable onto one of the
15 Serial IRQs.
General Purpose Input/Output.
I
Floppy on the Parallel Port Indication.
19
14MHz Clock CLOCKI
53,65,93
18
7,31, 60,76
VCC (Note 8)
VTR (Note 8)
VSS
VCC
VTR
VSS
CLOCK PIN (1)
IS
14.318MHz Clock Input.
POWER PINS (8)
+3.3 Volt Supply Voltage.
+3.3 Volt Standby Voltage.
Ground.
Note: The "n" as the first letter of a symbol indicates an "Active Low" signal.
Note 1: Buffer types per function on multiplexed pins are separated by a slash “/”. Buffer types in parenthesis
represent multiple buffer types for a single pin function.
Note 2: The nLPCPD pin may be tied high.
Note 3: The FDD output pins multiplexed in the PARALLEL PORT INTERFACE are OD drivers only and are not
affected by the FDD Output Driver Controls (see subsection CR05 in the Configuration section).
Note 4: Active (push-pull) output drivers are required on these pins in the enhanced parallel port modes.
Note 5: These pins require external pullups when the XRD# and XWR# functions are used.
Note 6: The open-drain selection as a buffer type applies to GP17 and GP20.
Note 7: The GP11/SYSOPT pin requires an external pulldown resistor to put the base IO address for configuration
at 0x02E. An external pullup resistor is required to move the base IO address for configuration to 0x04E.
Note 8: VCC must not be greater than 0.5V above VTR.
SMSC DS – LPC47N267
Page 14
Rev. 10/23/2000

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