LPC1830FET256 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC1830FET256

32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller

NXP Semiconductors. 

NXP Semiconductors

LPC1850/30/20/10

32-bit ARM Cortex-M3 microcontroller

 Three PLLs allow CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the

third PLL can be used as audio PLL.

 Clock output.

 Configurable digital peripherals:

 State Configurable Timer (SCT) subsystem on AHB.

 Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like timers, SCT, and ADC0/1.

 Serial interfaces:

 Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.

 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

 One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY (USB0).

 One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to an external high-speed PHY (USB1).

 USB interface electrical test software included in ROM USB stack.

 Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support UART synchronous mode and a

smart card interface conforming to ISO7816 specification.

 Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller

excludes operation of all other peripherals connected to the same bus bridge See

Figure 1 and Ref. 1.

 Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

 One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1 Mbit/s.

 One standard I2C-bus interface with monitor mode and standard I/O pins.

 Two I2S interfaces with DMA support, each with one input and one output.

 Digital peripherals:

 External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,

and SDRAM devices.

 LCD controller with DMA support and a programmable display resolution of up to

1024 H  768 V. Supports monochrome and color STN panels and TFT color

panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel

mapping.

 Secure Digital Input Output (SD/MMC) card interface.

 Eight-channel General-Purpose DMA controller can access all memories on the

AHB and all DMA-capable AHB slaves.

 Up to 164 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors.

 GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

LPC1850_30_20_10

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6.1 — 7 February 2013

© NXP B.V. 2013. All rights reserved.

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