LPC1315FBD48 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

LPC1315FBD48

32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM

NXP Semiconductors. 

NXP Semiconductors

Table 3. Pin description (LPC1315/16/17 - no USB)

Symbol

LPC1315/16/17/45/46/47

32-bit ARM Cortex-M3 microcontroller

Description

VREFP

VSSA

VDD

VSS

64 - -

55 - -

10; 8; 6;

33; 44 29

58

7; 5; 33

54 41

-

-

ADC positive reference voltage: This should be nominally

the same voltage as VDDA but should be isolated to

minimize noise and error. Level on this pin is used as a

reference for ADC. This pin should be tied to 3.3 V if the

ADC is not used.

-

-

Analog ground: 0 V reference. This should nominally be

the same voltage as VSSProduct data sheet but should be

isolated to minimize noise and error.

-

-

Supply voltage to the internal regulator and the external

rail. On LQFP48 and HVQFN33 packages, this pin is also

connected to the 3.3 V ADC supply and reference

voltage.

-

-

Ground.

[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;

F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.

[2] See Figure 33 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode.

[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 32).

[4] I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.

[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 32);

includes high-current output driver.

[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.

When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 32); includes

programmable digital input glitch filter.

[7] WAKEUP pin. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and

analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 32);

includes digital input glitch filter.

[8] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded

(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.

LPC1315_16_17_45_46_47

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 20 September 2012

© NXP B.V. 2012. All rights reserved.

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