LS7366-S View Datasheet(PDF) - LSI Corporation
Part Name
Description
Manufacturer
LS7366-S Datasheet PDF : 10 Pages
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CNTR. The CNTR is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from
the quadrature clocks applied at the A and B inputs, or alternatively, in non-quadrature mode, pulses applied at the A input. By
means of IR intructions the CNTR can be cleared, loaded from the DTR or in turn, can be transferred into the OTR. The “clear CNTR”
and the “load CNTR” commands in the ”range-limit” mode, however have limitations. In this mode when the CNTR is frozen in up count
direction at CNTR = DTR, a “clear CNTR” command will only function if the count direction is reversed from up to down. Similarly,
in the down direction at CNTR = 0, a “load CNTR” command will only function if the direction is reversed from down to up.
OTR. The OTR is a software configuration 8, 16, 24 or 32-bit register which can be read back on the MISO output.
Since instantaneous CNTR value is often needed to be read while the CNTR continues to count, the OTR serves as a
convenient dump site for instantaneous CNTR data which can then be read without interfering with the counting process.
STR. The STR is an 8-bit status register which stores
count related status information.
CY BW CMP IDX CEN PLS U/D S
7
6
5
4
3
210
CY: Carry (CNTR overflow) latch
BW: Borrow (CNTR underflow) latch
CMP: Compare (CNTR = DTR) latch
IDX: Index latch
CEN: Count enable status: 0: counting disabled,
1: counting enabled
PLS: Power loss indicator latch; set upon power up
U/D: Count direction indicator: 0: count down, 1: count up
S: Sign bit. 1: negative, 2: positive
A “CLR STR” command to IR resets all status bits except CEN
and U/D. In quadrature mode, if the quadrature clocks have
been halted, the status bits CY, BW and CMP are not affected
by a “CLR STR” command under the following conditions:
CY: If CNTR = FFFFFFFF with status bit U/D = 1
BW: If CNTR = 0 with status bit U/D = 0
CMP: If CNTR = DTR
In non-quadrature mode the same rules apply if input A is held at
logic low.
IR. The IR is an 8-bit register that fetches instruction bytes from
the received data stream and executes them to perform such
functions as setting up the operating mode for the chip (load the
MDR) and data transfer among the various registers.
B7 B6 B5 B4 B3 B2 B1 B0
B2 B1 B0 = XXX (Don’t care)
B5 B4 B3 = 000: Select none
= 001: Select MDR0
= 010: Select MDR1
= 011: Select DTR
= 100: Select CNTR
= 101: Select OTR
= 110: Select STR
= 111: Select none
B7 B6 = 00: CLR register
= 01: RD register
= 10: WR register
= 11: LOAD register
The actions of the four functions, CLR, RD, WR and LOAD are elaborated in Table 1.
Number of Bytes OP Code
1
CLR
2 to 5
RD
2 to 5
WR
1
LOAD
TABLE 1
Register
MDR0
MRD1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
Operation
Clear MDR0 to zero
Clear MDR1 to zero
None
Clear CNTR to zero
None
Clear STR to zero
Output MDR0 serially on TXD (MISO)
Output MDR1 serially on TXD (MISO)
None
Transfer CNTR to OTR, then output OTR serially
on TXD (MISO)
Output OTR serially on TXD (MISO)
Output STR serially on TXD (MISO)
Write serial data at RXD (MOSI) into MDR0
Write serial data at RXD (MOSI) into MDR1
Write serial data at RXD (MOSI) into DTR
None
None
None
None
None
None
Transfer DTR to CNTR in “parallel”
Transfer CNTR to OTR in “parallel”
7366-012405-3
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