Item
Symbol
φROG, φCLK pulse timing
t1
φROG, φCLK pulse timing
t3
φROG pulse high level period
t2
φCLK pulse high level period
t4
φCLK pulse low level period
t5
φRS pulse low level period
t6
φCLK, φRS pulse timing
t7
Input clock pulse rise/fall time
t8, t9
Input clock pulse voltage
High level
Low level
VφCLK, VφROG
VφRS
Signal output delay time
t10
Internal φRS
t11
t12
External φRS
t13
∗1 Recommended condition during φCLK = 1MHz.
ILX506
Min. Typ.
Max. Unit
100 200
—
ns
800 1000
—
ns
800 1000
—
ns
40 500∗1
—
ns
40 500∗1
—
ns
25 100∗1
—
ns
60 550∗1 10 + t4 + t5 ns
—
5
10
ns
4.5
5.0
5.5
V
0
—
0.5
V
—
95
—
ns
—
70
—
ns
—
45
—
ns
—
60
—
ns
– 10 –