LT3582 View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LT3582
Linear Technology
LT3582 Datasheet PDF : 28 Pages
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LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
I2C Interface
The LT3582 series contains an I2C compatible interface
with reduced input threshold voltages to allow for direct
communication with low voltage digital ICs (see Electri-
cal Characteristics). I2C communication is disabled when
SHDN is low. After SHDN rises, I2C communication is
re-enabled after a delay of 64μs (typical). The chip is a
read-write slave device which allows the user to read the
current settings and, for the LT3582, write new ones. Most
settings can be made permanent via the One-Time-Pro-
grammable memory. The chip will always enable using the
data stored in OTP and the LT3582 can be reconfigured
after power-up.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a
START condition by transitioning SDA from high to low
while SCL is high, as shown in Figure 1. When the master
has finished communicating with the slave, it issues a STOP
condition by transitioning SDA from low to high while SCL
is high. The bus is then free for another transmission.
ACKnowledge
The acknowledge signal (ACK) is used in handshaking
between transmitter and receiver to indicate that the most
recent byte of data was received. The transmitter always
releases the SDA line during the acknowledge clock pulse.
When the slave is the receiver, it pulls down the SDA line
so that it remains LOW during this pulse to acknowledge
receipt of the data. If the slave fails to acknowledge by
leaving SDA high, then the master may abort the transmis-
sion by generating a STOP condition. When the master
is receiving data from the slave, the master pulls down
the SDA line during the clock pulse to indicate receipt of
the data. After the last byte has been received the master
leaves the SDA line HIGH (not acknowledge) and issues a
stop condition to terminate the transmission.
Device Addressing
The LT3582 series supports two 7-bit chip addresses
depending on the logic state of the CA pin. The addresses
are 0110 001 (CA=1) and 1000 101 (CA=0). Also, there
are seven internal data byte locations as shown in Table
1. OTP0-OTP2 are the OTP memory bytes. REG0-REG2
are the corresponding volatile registers used for storing
alternate settings. Finally, the Command Register (CMDR)
is used for additional control of the chip.
All data bytes can be read from their assigned register
addresses. Since they share the same register addresses,
reads of the OTP and REG data bytes are differentiated
by their corresponding RSEL (Register Select) bits in the
SDA
A6 - A0
B7 - B0
B7 - B0
SCL
S
1-7
8
9
START
CHIP
CONDITION ADDRESS
R/W ACK
1-7
8
9
DATA
ACK
Figure 1. Data Transfer over I2C Bus
1-7
8
9
P
DATA
ACK
STOP
CONDITION
3582512 F01
3582512f
11
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