LTC1320CS View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC1320CS Datasheet PDF : 8 Pages
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LTC1320
PI FU CTIO S
RXEN (Pin 5): Receiver Enable (TTL Compatible). A high
level on this pin disables the receivers and three-states the
logic outputs; a low level allows normal operation. To
prevent erratic behavior at the receiver outputs during
shutdown, RXEN should be pulled high along with SD.
RXO (Pin 6): Inverting RS562 Single-Ended Receiver
Output.
RXO (Pin 7): Noninverting RS562 Single-Ended Receiver
Output.
RXDO (Pin 8): RS422 Differential Receiver Output.
GND (Pin 9): Ground Pin.
RXD+ (Pin 10): RS422 Differential Receiver Noninverting
Input. When this pin is ≥ 200mV above RXD –, RXDO will
be high; when this pin is ≥ 200mV below RXD –, RXDO will
be low.
RXD – (Pin 11): RS422 Differential Receiver Inverting
Input.
RXI (Pin 12): Noninverting RS562 Receiver Input. This
input controls the RXO output; it has no effect on the RXO
output.
RXI (Pin 13): Inverting RS562 Receiver Input. This input
controls the RXO output; it has no effect on the RXO
output.
VSS (Pin 14): Negative Supply. – 4.75 ≥ VSS ≥ – 5.25V. The
voltage on this pin must never exceed ground on power up
or power-down.
TXO (Pin 15): RS562 Single-Ended Driver Output.
TXD+ (Pin 16): RS422 Differential Driver Noninverting
Output.
TXD– (Pin 17): RS422 Differential Driver Inverting Output.
VDD (Pin 18): Positive Supply. 4.75V ≤ VDD ≤ 5.25V.
TEST CIRCUITS
TXD+
RL/2
VOD
RL/2
TXD
Figure 1
+
VOC
–
LTC1320 • F01
TXD+
CL1
TXD
RL
CL2
TXD–
Figure 2
LTC1320 • TCF02
OUTPUT
UNDER TEST
500Ω
VDD
CL
VSS
LTC1320 • F03
Figure 3
OUTPUT
UNDER TEST
TXI
CL
500Ω
VSS
Figure 4
LTC1320 • F04
TXO
RL
CL
LTC1320 • F05
Figure 5
OUTPUT
UNDER TEST
500Ω
VDD
CL
Figure 6
LTC1320 • F06
OUTPUT
UNDER TEST
CL
500Ω
LTC1320 • F07
Figure 7
4
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