LTC1753 View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTC1753

5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® III Processor

Linear Technology 

LTC1753

ELECTRICAL CHARACTERISTICS

The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.

VCC = 5V, PVCC = 12V, unless otherwise noted. (Note 3)

SYMBOL PARAMETER

CONDITIONS

MIN

GERR

gmERR

BWERR

IIMAX

ISS

ISSIL

ISSHIL

Error Amplifier Open-Loop DC Gain

Error Amplifier Transconductance

Error Amplifier – 3dB Bandwidth

IMAX Sink Current

Soft-Start Source Current

Maximum Soft-Start Sink Current

Under Current Limit

Soft-Start Sink Current Under Hard

Current Limit

(Note 7)

(Note 7)

COMP = Open (Note 11)

VIMAX = VCC

VSS = 0V, VIMAX = 0V, VIFB = VCC

VSENSE = VOUT, VIMAX = VCC, VIFB = 0V

(Notes 8, 9), VSS = VCC

VSENSE = 0V, VIMAX = VCC, VIFB = 0V

q 40

q 0.9

q 150

q – 16

q 30

q 20

tSSHIL

tPWRGD

tPWRBAD

tFAULT

VOTDD

VSHDN

tr, tf

t NOL

VIH

VIL

RSENSE

RVID

Hard Current Limit Hold Time

Power Good Response Time↑

Power Good Response Time↓

FAULT Response Time

Overtemperature Driver Disable

Shutdown

Driver Rise and Fall Time

Driver Nonoverlap Time

VID0 to VID4 Input High Voltage

VID0 to VID4 Input Low Voltage

SENSE Input Resistance

VID0 to VID4 Internal Pull-Up

Resistance

VSENSE = 0V, VIMAX = 4V, VIFB↓ from 5V

VSENSE↑ from 0V to Rated VOUT

q 0.5

VSENSE↓ from Rated VOUT to 0V

q 200

VSENSE↑ from Rated VOUT to VCC

q 200

OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) q 1.6

OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) q

(Figure 4)

q

(Figure 4)

q 30

q

2

q

q 10

ISINK

Digital Output Sink Current

q 10

TYP MAX

UNITS

54

dB

1.6

2.3 millimho

400

kHz

190 230

µA

– 12

–8

µA

60

150

µA

45

mA

500

µs

1

2

ms

500 1000

µs

500 1000

µs

1.7

1.8

V

0.8

V

90

150

ns

100

ns

V

0.8

V

108

kΩ

20

kΩ

mA

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: When IFB is taken below GND, it will be clamped by an internal diode.

This pin can handle input currents greater than 100mA below GND without

latchup. In the positive direction, it is not clamped to VCC or PVCC.

Note 3: All currents into device pins are positive; all currents out of the

device pins are negative. All voltages are referenced to ground unless

otherwise specified.

Note 4: The Power Good and FAULT trip thresholds are tested at the 1.8V

output voltage code. The Power Good and FAULT trip thresholds are

guaranteed by design for all other output voltage codes to the same

specification.

Note 5: The LTC1753 goes into the shutdown mode if VID0 to VID4 are

floating. Due to the internal pull-up resistors, there will be an additional

0.25mA/pin if any of the VID0 to VID4 pins are pulled low.

Note 6: Supply current in normal operation is dominated by the current

needed to charge and discharge the external FET gates. This will vary with

the LTC1753 operating frequency, supply voltage and the external FETs

used.

Note 7: The open-loop DC gain and transconductance from the SENSE pin to

COMP pin will be (GERR)(1.26/3.3) and (gmERR)(1.26/3.3) respectively.

Note 8: The current limiting amplifier can sink but cannot source current.

Under normal (not current limited) operation, the output current will be zero.

Note 9: Under typical soft current limit, the net soft-start discharge current

will be 60µA (ISSIL) + [– 12µA(ISS)] ≅ 48µA. The soft-start sink-to-source

current ratio is designed to be 5:1.

Note 10: When VID0 to VID4 are all HIGH, the LTC1753 will be forced to

shut down internally. The OUTEN trip voltages are guaranteed by design for

all other input codes.

Note 11: This parameter is guaranteed by design and correlation and is not

tested in production.

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