LTC2626CDD-1-TR View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC2626CDD-1-TR Datasheet PDF : 20 Pages
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LTC2606/LTC2616/LTC2626
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted.
LTC2626/LTC2626-1 LTC2616/LTC2616-1 LTC2606/LTC2606-1
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
AC Performance
tS
Settling Time (Note 6)
±0.024% (±1LSB at 12 Bits)
7
7
±0.006% (±1LSB at 14 Bits)
9
7
μs
9
μs
±0.0015% (±1LSB at 16 Bits)
10
μs
Settling Time for 1LSB Step ±0.024% (±1LSB at 12 Bits)
2.7
2.7
(Note 7)
±0.006% (±1LSB at 14 Bits)
4.8
±0.0015% (±1LSB at 16 Bits)
2.7
μs
4.8
μs
5.2
μs
Voltage Output Slew Rate
0.75
0.75
0.75
V/μs
Capacitive Load Driving
1000
1000
1000
pF
Glitch Impulse
At Mid-Scale Transition
12
12
12
nV•s
Multiplying Bandwidth
en
Output Voltage Noise Density At f = 1kHz
At f = 10kHz
180
180
120
120
100
100
180
kHz
120
nV/√Hz
100
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
15
15
μVP-P
TIMING CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (See Figure 1) (Notes 10, 11)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
tHD(STA)
Hold Time (Repeated) Start Condition
tLOW
Low Period of the SCL Clock Pin
tHIGH
High Period of the SCL Clock Pin
tSU(STA)
Set-Up Time for a Repeated Start Condition
tHD(DAT)
Data Hold Time
tSU(DAT)
Data Set-Up Time
tr
Rise Time of Both SDA and SCL Signals
tf
Fall Time of Both SDA and SCL Signals
tSU(STO)
Set-Up Time for Stop Condition
tBUF
Bus Free Time Between a Stop and Start Condition
t1
Falling Edge of 9th Clock of the 3rd Input Byte to
LDAC High or Low Transition
t2
LDAC Low Pulse Width
(Note 9)
(Note 9)
●
0
●
0.6
●
1.3
●
0.6
●
0.6
●
0
●
100
● 20 + 0.1CB
● 20 + 0.1CB
●
0.6
●
1.3
●
400
●
20
400
kHz
μs
μs
μs
μs
0.9
μs
ns
300
ns
300
ns
μs
μs
ns
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are defined from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is defined from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: Guaranteed by design and not production tested.
Note 5: Inferred from measurement at code 256 (LTC2606/LTC2606-1),
code 64 (LTC2616/LTC2616-1) or code 16 (LTC2626/LTC2626-1) and at
full-scale.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and
3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND.
Note 7: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half scale
and half scale – 1. Load is 2k in parallel with 200pF to GND.
Note 8: Maximum VIH = VCC(MAX) + 0.5V
Note 9: CB = capacitance of one bus line in pF.
Note 10: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 11: These specifications apply to LTC2606/LTC2606-1, LTC2616/
LTC2616-1, LTC2626/LTC2626-1.
26061626fb
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