LTC4261 View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC4261 Datasheet PDF : 32 Pages
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LTC2945
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD is from 4V to 80V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
I2C INTERFACE TIMING (Note 5)
CONDITIONS
MIN TYP MAX UNITS
fSCL(MAX)
tLOW
tHIGH
Maximum SCL Clock Frequency
Minimum SCL Low Period
Minimum SCL High Period
400
kHz
0.65
1.3
μs
50
600
ns
tBUF(MIN)
Minimum Bus Free Time Between Stop/Start
Condition
0.12
1.3
μs
tHD,STA(MIN) Minimum Hold Time After (Repeated) Start
Condition
140
600
ns
tSU,STA(MIN) Minimum Repeated Start Condition Set-Up
Time
30
600
ns
tSU,STO(MIN)
tHD,DATI(MIN)
tHD,DATO(MIN)
tSU,DAT(MIN)
tSP(MAX)
Minimum Stop Condition Set-Up Time
Minimum Data Hold Time Input
Minimum Data Hold Time Output
Minimum Data Set-Up Time
Maximum Suppressed Spike Pulse Width
30
600
ns
–100
0
ns
300
600
900
ns
30
100
ns
50
110
250
ns
tRST
Stuck Bus Reset Time
CX
SCL, SDAI Input Capacitance
SCL or SDAI Held Low
25
33
ms
5
10
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive. All voltages are referenced to
ground, unless otherwise noted.
Note 3: An internal shunt regulator limits the INTVCC pin to a minimum of
5.9V. Driving this pin to voltages beyond 5.9V may damage the part. This
pin can be safely tied to higher voltages through a resistor that limits the
current below 35mA.
Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of 5.9V.
Driving these pins to voltages beyond the clamp may damage the part. The
pins can be safely tied to higher voltages through resistors that limit the
current below 5mA.
Note 5: Guaranteed by design and not subject to test.
Note 6: TUE = (ACTUAL CODE −IDEAL CODE) × 100%
4096
where IDEAL CODE is derived from a straight line passing through Code 0
at 0V and Theoretical Code of 4096 at VFS.
Note 7: ΔSENSE is defined as VSENSE+ – VSENSE–
2945f
5
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