LTM4615IV View Datasheet(PDF) - Linear Technology

Part Name

Description

Manufacturer

LTM4615IV

Triple Output, Low Voltage DC/DC µModule Regulator

Linear Technology 

LTM4615

PIN FUNCTIONS

VIN1, VIN2 (J1-J5, K1-K5); (C1-C6, D1-D5): Power Input

Pins. Apply input voltage between these pins and GND

pins. Recommend placing input decoupling capacitance

directly between VIN pins and GND pins.

VOUT1, VOUT2 (K9-K12, L9-L12, M9-M12); (C9-C12,

D9-D12, E11-E12): Power Output Pins. Apply output load

between these pins and GND pins. Recommend placing

output decoupling capacitance directly between these pins

and GND pins. Review Table 4.

GND1, GND2, (H1, H7-H12, J6-J12, K6-K8 L1, L7-L8,

M1-M8); (A1-A12, B1, B7-B12, C7-C8, D6-D8, E1,

E8-E10): Power Ground Pins for Both Input and Output

Returns.

TRACK1, TRACK2 (L3, E3): Output Voltage Tracking Pins.

When the module is configured as a master output, then a

soft-start capacitor is placed on the RUN/SS pin to ground

to control the master ramp rate, or an external ramp can

be applied to the master regulator’s track pin to control it.

Slave operation is performed by putting a resistor divider

from the master output to the ground, and connecting the

center point of the divider to this pin on the slave regulator.

If tracking is not desired, then connect the TRACK pin to

VIN. Load current must be present for tracking. See the

Applications Information section.

FB1, FB2 (L6, E6): The Negative Input of the Switching

Regulators’ Error Amplifier. Internally, these pins are con-

nected to VOUT with a 4.99k precision resistor. Different

output voltages can be programmed with an additional

resistor between the FB and GND pins. Two power modules

can current share when this pin is connected in parallel

with the adjacent module’s FB pin. See the Applications

Information section.

FB3 (F6): The Negative Input of the LDO Error Amplifier.

Internally the pin is connected to LDO_OUT with a 4.99k

resistor. Different output voltages can be programmed with

an additional resistor between the FB3 and GND pins. See

the Applications Information section.

COMP1, COMP2 (L5, E5): Current Control Threshold

and Error Amplifier Compensation Point. The current

comparator threshold increases with this control voltage.

Two power modules can current share when this pin is

connected in parallel with the adjacent module’s COMP

pin. Each channel has been internally compensated. See

the Applications Information section.

PGOOD1, PGOOD2 (L4, E4): Output Voltage Power

Good Indicator. Open-drain logic output that is pulled to

ground when the output voltage is not within ±7.5% of

the regulation point.

RUN/SS1, RUN/SS2 (L2, E2): Run Control and Soft-Start

Pin. A voltage above 0.8V will turn on the module, and below

0.5V will turn off the module. This pin has a 1M resistor to

VIN and a 1000pF capacitor to GND. See the Applications

Information section for soft-start information.

SW1, SW2 (H2-H6, B2-B6): The switching node of the

circuit is used for testing purposes. This can be connected to

copper on the board for improved thermal performance.

LDO_IN (G1-G4): VLDO Input Power Pins. Place input

capacitor close to these pins.

LDO_OUT (G9-G12): VLDO Output Power Pins. Place

output capacitor close to these pins. Minimum 1mA load

is necessary for proper output voltage accuracy.

BOOST3 (E7): Boost Supply for Driving the Internal VLDO

NMOS Into Full Enhancement. The pin is use for testing

the internal boost converter. The output is typically 5V.

GND3 (F1-F5, F7, F9-F12, G6-G8): The power ground pins

for both input and output returns for the internal VLDO.

PGOOD3 (G5): VLDO Power Good Pin.

EN3 (F8): VLDO Enable Pin.

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