LXT9763 View Datasheet(PDF) - Intel

Part Name

Description

Manufacturer

LXT9763

Fast Ethernet 10/100 Hex Transceiver with Full MII

Intel 

Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763

Table 1. LXT9763 MII Signal Descriptions

Pin#

Symbol

Type1

Signal Description2

Data Interface Pins

79 TXD0_0

82 TXD0_1

83 TXD0_2

84 TXD0_3

Transmit Data - Port 0. 4-bit parallel data to be transmitted from port 0 is clocked in

I

synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error

signal is re-mapped to provide a fifth data bit.

60 TXD1_0

61 TXD1_1

62 TXD1_2

63 TXD1_3

Transmit Data - Port 1. 4-bit parallel data to be transmitted from port 1 is clocked in

I

synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error

signal is re-mapped to provide a fifth data bit.

42 TXD2_0

43 TXD2_1

44 TXD2_2

45 TXD2_3

Transmit Data - Port 2. 4-bit parallel data to be transmitted from port 2 is clocked in

I

synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error

signal is re-mapped to provide a fifth data bit.

24 TXD3_0

25 TXD3_1

26 TXD3_2

27 TXD3_3

Transmit Data - Port 3. 4-bit parallel data to be transmitted from port 3 is clocked in

I

synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error

signal is re-mapped to provide a fifth data bit.

6

TXD4_0

7

TXD4_1

8

TXD4_2

9

TXD4_3

Transmit Data - Port 4. 4-bit parallel data to be transmitted from port 4 is clocked in

I

synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error

signal is re-mapped to provide a fifth data bit.

196 TXD5_0

197 TXD5_1

198 TXD5_2

199 TXD5_3

Transmit Data - Port 5. 4-bit parallel data to be transmitted from port 5 is clocked in

I

synchronously to TX_CLK. In symbol mode (16.11 = 1), the port transmit error

signal is re-mapped to provide a fifth data bit.

77 TX_EN0

59 TX_EN1

41 TX_EN2

23 TX_EN3

5

TX_EN4

195 TX_EN5

I

Transmit Enable - Ports 0 - 5. Active High input enables respective port transmitter.

This signal must be synchronous to the TX_CLK.

75 TX_ER0/TXD0_4

57 TX_ER1/TXD1_4

39 TX_ER2/TXD2_4

21 TX_ER3/TXD3_4

3

TX_ER4/TXD4_4

191 TX_ER5/TXD5_4

Transmit Coding Error - Ports 0 - 5. Valid during 100 Mbps operation only. This

signal must be driven synchronously to TX_CLK. When High, forces the respective

port to transmit Halt (H) code group.

I

Transmit Data - Ports 0 - 5. During symbol mode operation (16.11 = 1), these

signals are re-mapped to provide the fifth data bit (TXDn_4) for their respective ports

(n).

76 TX_CLK0

58 TX_CLK1

40 TX_CLK2

22 TX_CLK3

4

TX_CLK4

194 TX_CLK5

Transmit Clock - Ports 0 - 5. 25 MHz for 100 Mbps operation, 2.5 MHz for 10 Mbps

O

operation. The transmit data and control signals must always be synchronized to

TX_CLK by the MAC. The LXT9763 samples these signals on the rising edge of

TX_CLK.

71 RXD0_0

70 RXD0_1

69 RXD0_2

66 RXD0_3

Receive Data - Port 0. Data received at network port 0 is output in 4-bit parallel

O nibbles, driven synchronously to RX_CLK. In symbol mode (16.11 = 1), the

receive error signals are re-mapped to provide a fifth data bit.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain

2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,

where X is the register number (0-32) and Y is the bit number (0-15).

Datasheet

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