A(18:0)
tAVAV
DQ(7:0)
Previous Valid Data
Assumptions:
1 . E and G < VIL (max) and W > VIH (min)
tA X Q X
Valid Data
tAVQV
Figure 4a. SRAM Read Cycle 1: Address Access
A(18:0)
E
DQ(7:0)
tETQV
tETQX
tEFQZ
DATA VALID
Assumptions:
1. G < VIL (max) and W > VIH (min)
Figure 4b. SRAM Read Cycle 2: Chip Enable - Controlled Access
A(18:0)
G
DQ(7:0)
Assumptions:
1 . E< VIL (max) and W > VIH (min)
tAVQV
tGLQX
tGLQV
DATA VALID
tG H Q Z
Figure 4c. SRAM Read Cycle 3: Output Enable - Controlled Access
7