M27V160-100B1TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M27V160-100B1TR Datasheet PDF : 15 Pages
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Figure 8. Programming and Verify Modes AC Waveforms
A0-A19
Q0-Q15
BYTEVPP
VCC
E
G
tAVEL
DATA IN
tQVEL
VALID
tEHQX
DATA OUT
tVPHAV
tGLQV
tVCHAV
tELEH
tQXGL
PROGRAM
VERIFY
M27V160
tGHQZ
tGHAX
AI00744
Figure 9. Programming Flowchart
VCC = 6.25V, VPP = 12.5V
n=0
NO
++n
= 25
YES
E = 50µs Pulse
NO
VERIFY
YES
++ Addr
FAIL
Last NO
Addr
YES
CHECK ALL WORDS
BYTEVPP =VIH
1st: VCC = 5V
2nd: VCC = 3V
AI00901B
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 52.5 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 9).
During programing and verify operation a MAR-
GIN MODE circuit is automatically activated to
guarantee that each cell is programed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE at VCC much higher than
3.6V provides the necessary margin to each pro-
grammed cell.
Program Inhibit
Programming of multiple M27V160s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
M27V160 may be common. A TTL low level pulse
applied to a M27V160’s E input and VPP at 12.5V,
will program that M27V160. A high level E input in-
hibits the other M27V160s from being pro-
grammed.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with E
at VIH and G at VIL, VPP at 12.5V and VCC at
6.25V.
9/15
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