V436664X24V View Datasheet(PDF) - Mosel Vitelic Corporation
Part Name
Description
Manufacturer
V436664X24V Datasheet PDF : 13 Pages
| |||
MOSEL VITELIC
SPD-Table for modules: (Continued)
Byte Num-
ber
Function Described
SPD Entry Value
28
Minimum Row Active to Row Active Delay tRRD 14 ns/15 ns/16 ns
29
Minimum RAS to CAS Delay tRCD
15 ns/20 ns
30
Minimum RAS Pulse Width tRAS
42 ns/45 ns
31
Module Bank Density (Per Bank)
512Mbyte
32
SDRAM Input Setup Time
1.5 ns/2.0 ns
33
SDRAM Input Hold Time
0.8 ns/1.0 ns
34
SDRAM Data Input Setup Time
1.5 ns/2.0 ns
35
SDRAM Data Input Hold Time
0.8 ns/1.0 ns
62-61
Superset Information (May be used in Future)
62
SPD Revision
Revision 2 / 1.2
63
Checksum for Bytes 0 - 62
64
Manufacturer’s JEDEC ID Code
Mosel Vitelic
65-71
Manufacturer’s JEDEC ID Code (cont.)
72
Manufacturing Location
1 = US, 2 = Taiwan
73-90
Module Part Number (ASCII)
V436664X24V
91-92
PCB Identification Code
Current PCB Revision
93
Assembly Manufacturing Date (Year)
Binary Coded year (BCD)
94
Assembly Manufacturing Date (Week)
Binary Coded week (BCD)
95-98
Assembly Serial Number
byte 95 = LSB, byte 98 =
MSB
99-125 Reserved
126
Intel Specification for Frequency
127
Supported Frequency
128+
Unused Storage Location
-75PC
0E
0F
2A
80
15
08
15
08
00
02
38
40
00
00
64
00
V436664X24V
Hex Value
-75
0F
14
2D
80
15
08
15
08
00
02
7D
40
00
-10PC
10
14
2D
80
20
10
20
10
00
12
EB
40
00
00
00
64
64
00
00
V436664X24V Rev. 1.0 January 2002
6
Share Link: 