M29W017D View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M29W017D

16 Mbit (2Mb x8, Uniform Block) 3V Supply Flash Memory

STMicroelectronics 

M29W017D

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation. During Bus Write

operations they represent the commands sent to

the Command Interface of the internal state ma-

chine.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, VIH, all other pins are ignored.

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to temporarily unprotect all Blocks that have been

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, VIL, for at least

tPLPX. After Reset/Block Temporary Unprotect

goes High, VIH, the memory will be ready for Bus

Read and Bus Write operations after tPHEL or

tRHEL, whichever occurs last. See the Ready/Busy

Output section, Table 13 and Figure 13, Reset/

Temporary Unprotect AC Characteristics for more

details.

Holding RP at VID will temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from VIH to VID must be slower than

tPHPHH.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

Ready/Busy is Low, VOL. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 13 and Figure

13, Reset/Temporary Unprotect AC Characteris-

tics.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

VCC Supply Voltage (2.7V to 3.6V). VCC pro-

vides the power supply for all operations (Read,

Program and Erase).

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This prevents Bus Write operations from ac-

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

the VCC Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power

supply. See Figure 10, AC Measurement Load Cir-

cuit. The PCB track widths must be sufficient to

carry the currents required during program and

erase operations, ICC3.

VSS Ground. VSS is the reference for all voltage

measurements.

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