M29W640FB View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M29W640FB Datasheet PDF : 72 Pages
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M29W640FT, M29W640FB
3 Bus operations
3 Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus Write,
Output Disable, Standby and Automatic Standby. See Table 3: Bus Operations, BYTE = VIL
and Table 4: Bus Operations, BYTE = VIH, for a summary. Typically glitches of less than 5ns on
Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Outputs will output the value, see Figure 8: Read Mode AC
Waveforms, and Table 13: Read AC Characteristics, for details of when the output becomes
valid.
3.2 Bus Write
Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.
A valid Bus Write operation begins by setting the desired address on the Address Inputs. The
Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or
Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command
Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output
Enable must remain High, VIH, during the whole Bus Write operation. See Figure 10: Write AC
Waveforms, Write Enable Controlled, Figure 11: Write AC Waveforms, Chip Enable Controlled,
and Table 14: Write AC Characteristics, Write Enable Controlled and Table 15: Write AC
Characteristics, Chip Enable Controlled, for details of the timing requirements.
3.3 Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4 Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs
pins are placed in the high-impedance state. To reduce the Supply Current to the Standby
Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current
level see Table 12: DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase Supply
Current, ICC3, for Program or Erase operations until the operation completes.
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