M2V28S20TP View Datasheet(PDF) - Mitsumi
Part Name
Description
Manufacturer
M2V28S20TP Datasheet PDF : 52 Pages
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SDRAM (Rev. 1.0E)
Jun. '99
MITSUBISHI LSIs
M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
PIN FUNCTION
CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
BA0,1
DQ0-7
Input
Input / Output
DQM
Input
Vdd, Vss
VddQ, VssQ
Power Supply
Power Supply
Master Clock:
All other inputs are referenced to the rising edge of CLK.
Clock Enable:
CKE controls internal clock. When CKE is low, internal clock for the
following cycle is ceased. CKE is also used to select auto /
selfrefresh. After self refresh mode is started, CKE becomes
synchronous input. Self refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable:
When DQM is high in burst write, Din for the current cycle is masked.
When DQM is high in burst read, Dout is disabled at the next but one
cycle.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
MITSUBISHI ELECTRIC
5
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