M2V56S20AKT View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M2V56S20AKT

256M Synchronous DRAM

Mitsumi 

SDRAM (Rev.1.01)

Single Data Rate

July '01

MITSUBISHI LSIs

M2V56S20/ 30/ 40 AKT -5, -6, -7

256M Synchronous DRAM

[ Read Interrupted by Precharge ]

A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is

minimum 1 CLK.

A PRE command to output disable latency is equivalent to the /CAS Latency.

Read interrupted by Precharge (BL=4)

CLK

Command

READ

PRE

CL=2

DQ

Command

DQ

Command

READ

Q0 Q1 Q2

PRE

Q0 Q1

READ PRE

DQ

Q0

CL=3

Command

DQ

Command

DQ

Command

DQ

READ

PRE

READ

Q0 Q1 Q2

PRE

READ PRE

Q0 Q1

Q0

MITSUBISHI ELECTRIC

19

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