SDRAM (Rev.1.01)
Single Data Rate
July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write interrupted by Write (BL=4)
CLK
Command
Write
Write Write
A0-9,11-12
Ya
Yb Yc
A10
0
0
0
BA0-1
00
00 10
DQ
Da0 Da1 Da2 Db0 Dc0 Dc1 Dc2 Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column access is allowed.
WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is
"Don't Care".
Write interrupted by Read (CL=2, BL=4)
CLK
Command ACT
Write
READ
A0-9,11-12 Xa
Ya
Yb
A10 Xa
0
0
BA0-1 00
00
00
DQ
Da0 Da1
Qb0 Qb1 Qb2 Qb3
don't care
MITSUBISHI ELECTRIC
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