M2V56S20AKT-5L View Datasheet(PDF) - Mitsumi
Part Name
Description
Manufacturer
M2V56S20AKT-5L Datasheet PDF : 49 Pages
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SDRAM (Rev.1.01)
Single Data Rate
July '01
AC TIMING REQUIREMENTS
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
(Ta=0 ~ 70¡C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level:
1.4V
Symbol
Parameter
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
CLK cycle time
CL=2
CL=3
CLK High pulse width
CLK Low pulse width
Transition time of CLK
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
Refresh Cycle time
Row to Column Delay
-5
Min. Max.
7.5
6
2.5
2.5
1
10
1.5
0.8
60
60
15
Limits
-6
Min. Max.
10
7.5
2.5
2.5
1
10
1.5
0.8
67.5
75
20
-7
Min. Max.
10
10
3
3
1
10
2
1
70
80
20
Unit Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRAS Row Active time
42 120000 45 120000 50 120000 ns
tRP
tWR
tRRD
tRSC
tREF
Row Precharge time
Write Recovery time
ACT to ACT Delay time
Mode Register Set Cycle
time
Average Refresh Interval
15
20
20
ns
12
15
20
ns
12
15
20
ns
12
15
20
ns
7.8
7.8
7.8 µs
CLK
Signal
1.4V
1.4V
AC timing is referenced to the
input signal crossing through
1.4V.
MITSUBISHI ELECTRIC
31
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