SDRAM (Rev.1.01)
Single Data Rate
July '01
MITSUBISHI LSIs
M2V56S20/ 30/ 40 AKT -5, -6, -7
256M Synchronous DRAM
Self Refresh
CLK
/CS
/RAS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
tRFC
tRP
/CAS
/WE
CKE
DQM
A0-9,11
X
A10
X
A12
X
BA0,1
0
DQ
PRE ALL Self Refresh Entry
Self Refresh Exit
All banks must be idle before REFS is issued.
ACT#0
Italic paramater shows minimum case
MITSUBISHI ELECTRIC
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