M2V56S20TP View Datasheet(PDF) - Mitsumi

Part Name

Description

Manufacturer

M2V56S20TP

256M Synchronous DRAM

Mitsumi 

SDRAM (Rev.1.1)

Single Data Rate

Feb.2000

MITSUBISHI LSIs

M2V56S20/ 30/ 40/ TP -6, -7, -8

256M Synchronous DRAM

Some of contents are subject to change without notice.

DESCRIPTION

M2V56S20TP is a 4-bank x 16777216-word x 4-bit,

M2V56S30TP is a 4-bank x 8388608-word x 8-bit,

M2V56S40TP is a 4-bank x 4194304-word x 16-bit,

synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge

of CLK. The M2V56S20/30/40TP achieve very high speed data rate up to 100MHz (-7/-8) , 133MHz

(-6), and are suitable for main memory or graphic memory in computer systems.

FEATURES

- Single 3.3v±0.3V power supply

- Max. Clock frequency 100MHz(-7/-8), 133MHz (-6)

- Fully Synchronous operation referenced to clock rising edge

- Single Data Rate

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2/3 (programmable)

- Burst length- 1/2/4/8/full page (programmable)

- Burst type- sequential / interleave (programmable)

- Random column access

- Auto precharge / All bank precharge controlled by A10

- 8192 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- LVTTL Interface

- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch

M2V56S20/30/40TP-6

M2V56S20/30/40TP-7

M2V56S20/30/40TP-8

Max. Frequency

@CL2

100MHz

100MHz

77MHz

Max. Frequency

@CL3

133MHz

100MHz

100MHz

Standard

PC133 (CL3)

PC100 (CL2)

PC100 (CL3)

MITSUBISHI ELECTRIC

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