M2V56S20TP View Datasheet(PDF) - Mitsumi
Part Name
Description
Manufacturer
M2V56S20TP Datasheet PDF : 49 Pages
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SDRAM (Rev.1.1)
Single Data Rate
Feb.2000
MITSUBISHI LSIs
M2V56S20/ 30/ 40/ TP -6, -7, -8
256M Synchronous DRAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level:
1.4V
Symbol
Parameter
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tREF
CLK cycle time
CL=2
CL=3
CLK High pulse width
CLK Low pulse width
Transition time of CLK
Input Setup time (all inputs)
Input Hold time (all inputs)
Row Cycle time
Refresh Cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
ACT to ACT Delay time
Mode Register Set Cycle time
Average Refresh Interval
-6
Min. Max.
10
7.5
2.5
2.5
1
10
1.5
0.8
67.5
75
20
45 120000
20
15
15
15
7.8
Limits
-7
Min. Max.
10
10
3
3
1
10
2
1
70
80
20
50 120000
20
20
20
20
7.8
-8
Unit Note
Min. Max.
13
ns
10
ns
3
ns
3
ns
1
10 ns
2
ns
1
ns
70
ns
80
ns
20
ns
50 120000 ns
20
ns
20
ns
20
ns
20
ns
7.8 µs
CLK
Signal
1.4V
1.4V
AC timing is referenced to the
input signal crossing through 1.4V.
MITSUBISHI ELECTRIC
31
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