M34551E4-XXXFP View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part Name

Description

Manufacturer

M34551E4-XXXFP

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

4551 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for

INFRARED REMOTE CONTROL TRANSMITTER

(6) Interrupt control register

q Interrupt control register V1

Interrupt enable bits of external 0, timer 1 and timer 2 are

assigned to register V1. Set the contents of this register

through register A with the TV1A instruction. The TAV1

instruction can be used to transfer the contents of register

V1 to register A.

Table 6 Interrupt control register

Interrupt control register V1

at reset : 00002

at power down : 00002

R/W

V13 Timer 2 interrupt enable bit

0 Interrupt disabled (SNZT2 instruction is valid)

1 Interrupt enabled (SNZT2 instruction is invalid)

V12 Timer 1 interrupt enable bit

0 Interrupt disabled (SNZT1 instruction is valid)

1 Interrupt enabled (SNZT1 instruction is invalid)

V11 Not used

0

This bit has no function, but read/write is enabled.

1

V10 External 0 interrupt enable bit

0 Interrupt disabled (SNZ0 instruction is valid)

1 Interrupt enabled (SNZ0 instruction is invalid)

Note: “R” represents read enabled, and “W” represents write enabled.

(7) Interrupt sequence

Interrupts occur only when the respective INTE flag, interrupt

enable bits (V10–V13), and interrupt request flags (EXF0, T1F,

T2F) are “1.” The interrupt actually occurs 2 to 3 machine

cycles after the cycle in which all three conditions are satisfied.

The interrupt occurs after 3 machine cycles only when the

three interrupt conditions are satisfied on execution of other

than one-cycle instructions (Refer to Figure 16).

q When an interrupt request flag is set after its interrupt is enabled

1 machine cycle

System clock (STCK)

Interrupt enable

“1”

flag (INTE)

“0”

EI instruction

execution cycle

Interrupt enabled state

Interrupt disabled state

External

interrupt

INT pin “H”

“L”

“1”

EXF0 “0”

flag

Retaining level for 4 cycles or

more of STCK is necessary.

Interrupt activated

condition is satisfied.

Timer 1

and

Timer 2

interrupts

“1”

T1F, T2F “0”

flags

Flag cleared

2 to 3 machine cycles

(Note 1, 2)

Software starts from the

interrupt address.

Notes 1: The address is stacked to the last cycle.

2: This interval of cycles depends on the executed instruction at the time when each interrupt activated

condition is satisfied.

Fig. 16 Interrupt sequence

15

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