M41T64 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M41T64 Datasheet PDF : 41 Pages
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Clock operation
M41T62/63/64/65
3.1
RTC registers
The M41T6x user interface is comprised of 16 memory mapped registers which include
clock, calibration, alarm, watchdog, flags, and square wave control. The eight clock
counters are accessed indirectly via a set of buffer/transfer registers while the other eight
registers are directly accessed. Data in the clock and alarm registers is in BCD format.
Figure 20. Buffer/transfer registers
2
I2C
I2C
INTERFACE
CLOCK COUNTERS ARE
ACCESSED INDIRECTLY
THRU BUFFER/TRANSFER
REGISTERS
AT START OF READ, UDATES FROM COUNTERS
ARE HALTED AND PRESENT TIME IS FROZEN
IN BUFFER/TRANSFER REGISTERS.
32KHz
OSC
READ / WRITE
BUFFER
TRANSFER
REGISTERS
SECONDS
MINUTES
HOURS
DAY-OF-WEEK
DATE
MONTHS
YEARS
CENTURIES
DIVIDE BY
32768
1 Hz
COUNTER
COUNTER
COUNTER
COUNTER COUNTER
COUNTER
COUNTER
DATA TRANSFERRED
OUT OF I2C INTERFACE
ON 8th FALLING EDGE
OF SCL (ON WRITES)
NON-CLOCK REGISTERS
ARE DIRECTLY ACCESSED
NON-CLOCK
REGISTERS
CALIBRATION
WATCHDOG
FLAGS
COUNTER
ON WRITES, DATA TRANSFERRED
FROM BUFFERS TO COUNTERS
WHEN ADDRESS POINTER
INCREMENTS TO 8 OR WHEN I2C
STOP CONDITION IS RECEIVED
AM04890v1
Updates
During normal operation when the user is not accessing the device, the buffer/transfer
registers are kept updated with a copy of the RTC counters. At the start of an I2C read or
write cycle, the updating is halted and the present time is frozen in the buffer/transfer
registers.
Reads of the clock registers
By halting the updates at the start of an I2C access, the user is ensured that all the data
transferred out during a read sequence comes from the same instant in time.
18/41
Doc ID 10397 Rev 14
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