M470L6423EN0-CLB3 View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
M470L6423EN0-CLB3 Datasheet PDF : 13 Pages
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512MB Unbuffered SODIMM(based on sTSOP)
DDR SDRAM
AC Operating Conditions
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
Min
Max
Unit
VIH(AC) VREF + 0.31
V
VIL(AC)
VREF - 0.31
V
VID(AC)
0.7
VDDQ+0.6
V
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note
3
3
1
2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
Output
RT=50Ω
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
Parameter
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0, CKE1)
Input capacitance(CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7)
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
M470L6423EN0
Unit
Min
Max
38
47
pF
38
47
pF
36
44
pF
36
40
pF
12
14
pF
12
14
pF
12
14
pF
Rev. 1.3 March. 2004
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