M470L3223DT0 View Datasheet(PDF) - Samsung
Part Name
Description
Manufacturer
M470L3223DT0 Datasheet PDF : 16 Pages
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M470L3223DT0
Parameter
Mode register set cycle time
Control & Address input pulse width
(for each input)
DQ & DM input pulse width(for each input)
Exit self refresh to non read command
Exit self refresh to read command
Refresh interval time
64Mb, 128Mb
256Mb
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
Auto Precharge Write recovery +
Precharge time
Symbol
tMRD
-TCB3(DDR333)
Min
Max
12
tIPW
2.2
tDIPW
1.75
tXSNR
75
tXSRD
200
15.6
tREFI
7.8
tQH tHP-tQHS
-
tHP
tCLmin
or tCHmin
-
tQHS
0.55
tRAP
tRCD or
tRAS min
tDAL (tWR/tCK) +
(tRP/tCK)
Unit Note
ns
ns
ns
ns
tCK
us 1
us 1
ns 4
ns
ns
ns 3
tCK 5
1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. For registered DINNs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
5. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
Rev. 0.0 Dec. 2001
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