M464S3354BTS-CL7A View Datasheet(PDF) - Samsung

Part Name

Description

Manufacturer

M464S3354BTS-CL7A

SDRAM Unbuffered SODIMM

Samsung 

256MB, 512MB Unbuffered SODIMM

SDRAM

PIN CONFIGURATION DESCRIPTION

Pin

CLK

CS

Name

System clock

Chip select

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

CKE

Clock enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+tSS prior to valid command.

A0 ~ A12 Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12

Column address : (x16 : CA0 ~ CA9)

BA0 ~ BA1 Bank select address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

RAS

Row address strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS

Column address strobe

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

WE

Write enable

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

DQM0 ~ 7 Data input/output mask

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

DQ0 ~ 63

VDD/VSS

Data input/output

Power supply/ground

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Rev. 1.2 March 2004

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